The present invention relates to a correlated double sampling circuit having a clamping circuit and a sample hold circuit and to an amplification type solid state imaging device employing the correlated double sampling circuit.
Conventionally, as an amplification type solid state imaging device, there has been proposed one that does not read a signal charge itself generated in each pixel but operates to convert the signal charge into a voltage signal (or a current signal) inside the pixel, amplify the signal and thereafter read the voltage signal (or the current signal) by means of a scanning circuit. The pixel section of this amplification type solid state imaging device is classified into a horizontal type in which a photoelectric conversion section and an amplifying section are arranged in a planar style and a vertical type in which a photoelectric conversion section and an amplifying section are arranged in a cubic style.
As an amplification type solid state imaging device of the aforementioned horizontal type, there is known one of the APS (Active Pixel Sensor) type shown in FIG. 14. Referring to FIG. 14, a signal charge generated in a photoelectric conversion section 101 is transferred to a gate of a transistor 103 via a transistor 102 to a gate of which a voltage xcfx86T is applied and made to be a voltage signal. The transistor 103 executes impedance conversion (current amplification) to read a signal Vsig via a pixel selecting switch 104 to a gate of which a voltage xcfx86X is applied. Immediately before or after reading this signal Vsig, the signal charges accumulated in the gate of the transistor 103 are discharged to a power voltage VD side by a reset transistor 105 to a gate of which a voltage xcfx86R is applied.
As an amplification type solid state imaging device of the vertical type, one of the CMD (Charge Modulation Device) type shown in FIG. 15 is known. Referring to FIG. 15, in a transistor 111, signal charges generated through the photoelectric conversion are accumulated under the gate. Subsequently, by applying a read voltage xcfx86X to the gate of the transistor 111, a change in the characteristics of the transistor 111 due to the signal charges is read as the output signal Vsig. Thus, the transistor 111 executes the photoelectric conversion, amplification and pixel selection. A reset operation is achieved by discharging the signal charges to the substrate side with a voltage xcfx86R that is sufficiently higher than in the reading stage applied to the gate. Therefore, a three-valued voltage pulse xcfx86X/xcfx86R is necessary for driving.
The pixel section of each of the aforementioned amplification type solid state imaging devices shown in FIG. 14 and FIG. 15 is represented by a common schematic diagram as shown in FIG. 16. In FIG. 16, the reference numeral 131 denotes a pixel section for executing the operations of photoelectric conversion, reading and resetting. The reading of the pixel section 131 is controlled by the voltage "PHgr"X of a signal line 106, and the resetting is controlled by the voltage "PHgr"R of a signal line 107. Then, the pixel section 131 outputs the amplified signal Vsig via a vertical signal line 108.
FIG. 17 shows a schematic view of an amplification type solid state imaging device (two-dimensional image sensor) employing the aforementioned pixel section. Referring to FIG. 17, a two-dimensional pixel region 140 is constructed of the pixel sections 131, a first vertical scanning circuit 141 and a second vertical scanning circuit 142. The read operation of the pixel section 131 is controlled by a signal 143 from the first vertical scanning circuit 141, while the resetting operation is controlled by a signal 144 from the second vertical scanning circuit 142. An output signal of the pixel section 131 is outputted to a vertical signal line 145 and thereafter conducted to a correlated double sampling circuit provided for each vertical signal line 145. A difference between a light-receiving signal obtained in a reading stage and a reference signal after the resetting is outputted from the correlated double sampling circuit. In is herein noted that the light-receiving signal and the reference signal possibly take either one of two cases depending on which one comes first. According to the output of the difference, the variation in a threshold value per pixel section 131 is canceled, by which a fixed pattern noise (referred to as FPN hereinafter) of each pixel section 131 is suppressed. It is to be noted that the aforementioned correlated double sampling circuit is constructed of a clamping circuit (a clamping capacitor 146 and a clamping switch 147) and a sample hold circuit (a sample hold switch 148 and a sample hold capacitor 149).
In the aforementioned correlated double sampling circuit, the vertical signal line 145 is connected to the sample hold switch 148 via the clamping capacitor 146 and connected to a clamping potential VCP via the clamping switch 147. The clamping operation to the clamping potential VCP is executed by making a pulse xcfx86C1 have high level in the reading stage of the light-receiving signal from the pixel section 131. The sample hold operation is executed by making a pulse xcfx86S1 have high level in the reading stage of the reference signal from the pixel section 131. Then, the signal from the sample hold switch 148 is held in the sample hold capacitor 149 and amplified by an amplifier circuit 155. The signal amplified by the amplifier circuit 155 is conducted to a horizontal signal line 164 via a horizontal selection switch 156 controlled by a signal 161 from a horizontal scanning circuit 160, while the horizontal signal line 164 outputs a signal OS via an amplifier circuit 169.
As described above, according to the amplification type solid state imaging device (two-dimensional image sensor) shown in FIG. 17, the correlated double sampling circuit provided for each vertical signal line 145 suppresses the FPN caused by the variation in the threshold value per pixel section 131. However, the amplifier circuit 155 provided for each vertical signal line 145 is accompanied by variations in an offset level and gain. The variations, which are random in the horizontal direction and common in the vertical direction of the image, causes a significant vertical-stripe-shaped FPN in terms of a video image, significantly impairing the image quality. Furthermore, the horizontal selection switch 156 is accompanied by variations in conductance, and this becomes a factor of the vertical-stripe-shaped FPN.
As a method for solving the aforementioned vertical-stripe-shaped FPN, there has been proposed the amplification type solid state imaging device (two-dimensional image sensor) shown in FIG. 18 (Japanese Patent Laid-Open Publication No. HEI 10-173997). In this amplification type solid state imaging device, the two-dimensional pixel region has the same construction as the pixel region 140 shown in FIG. 17, and therefore, neither drawing nor description is provided for the region. The correlated double sampling circuit provided for each vertical signal line 145 has the same construction as that shown in FIG. 17. A difference to the amplification type solid state imaging device shown in FIG. 17 is that the amplifier circuit 155 provided for each vertical signal line 145 has two inputs, one being a signal 153 from the correlated double sampling circuit and the other being a reference voltage signal Vref. Furthermore, a second CDS (correlated double sampling) circuit 168 is provided at the terminal of the horizontal signal line 164.
In the amplification type solid state imaging device (two-dimensional image sensor) having the aforementioned construction, signals from the amplifier circuits 155 are sequentially read to the horizontal signal line 164 by the switches 156 driven by a pulse xcfx86H(j) or the like from the horizontal scanning circuit 160. It is to be noted that the input of the amplifier circuit 155 is switched from the signal 153 to the reference signal 154 somewhere in each reading period. Therefore, on the horizontal signal line 164, the signal of the vertical signal line 145 and the reference signal are sequentially obtained in pairs. The variations in the characteristics of the amplifier circuits 155 and the horizontal selection switches 156 commonly exist in the each of these pairs of signals. Therefore, if a difference between the signal of the vertical signal line 145 and the reference signal is taken by a second CDS circuit 168, then there is obtained the net signal component from which the difference in characteristics between the amplifier circuits 155 and the horizontal selection switches 156 are removed. With this arrangement, the vertical-stripe-shaped FPN is prevented.
However, in the case of the amplification type solid state imaging device (two-dimensional image sensor) shown in FIG. 18, there are the problems as follows. That is, the clamping switch 147 provided for each vertical signal line 145 has a slight variation in the characteristics thereof. Therefore, the feedthrough level in the clamping operation stage varies every vertical signal line 145. Furthermore, the sample hold switch 148 provided for each vertical signal line 145 also has a slight variation in the characteristics. Therefore, the feedthrough level in the sample hold operation stage also varies every vertical signal line 145. The variations in the feedthrough level become the factors that cause the vertical-stripe-shaped FPN.
In view of the above, as another method for solving an aforementioned vertical-stripe-shaped FPN, there is proposed an amplification type solid state imaging device (two-dimensional image sensor) shown in FIG. 19 (Japanese Patent Laid-Open Publication No. HEI 10-145681). As shown in FIG. 19, a pair of capacitors 191 and 192 are connected to each vertical signal line 145 via a switch 190, and the other end (output terminal) of each of the capacitors 191 and 192 is connected to the reference voltage Vref via switches 193 and 194. The output terminal of the capacitor 191 is branched and inputted to the amplifier circuit 155. The signal from the amplifier circuit 155 is controlled by the pulse signal 161, i.e., "PHgr"H(j), the pulse signal 162, i.e., "PHgr"A2(j) and so on from the horizontal scanning circuit 160 and sequentially outputted to the horizontal signal line 164. Subsequently, only the net signal component is obtained by the second CDS circuit 168.
FIGS. 20A through 20E show timing charts for explaining the operation of the amplification type solid state imaging device shown in FIG. 19. It is to be noted that the following description is based on the condition that the light-receiving signal comes first and the reset signal comes later. By turning on the switch 193 and turning on the switch 190 (shown in FIGS. 20A and 20B) at a time t1 within a horizontal blanking period, the potential of a portion (V2) becomes a light-receiving signal Vf of the pixel element (shown in FIG. 20D), and the potential of a portion (V3) becomes Vref (shown in FIG. 20E). Subsequently, by sequentially turning off the switches 190 and 193, the (V2) potential becomes Vfxe2x88x92xcex94V1xe2x88x92xcex94V2, while the (V3) potential becomes Vrefxe2x88x92xcex94V2 (shown in FIGS. 20D and 20E). It is to be noted that xcex94V1 is the feedthrough level of the switch 190 at (V2), and xcex94V2 is the feedthrough level of the switch 193 at (V3). Through the above operations, the capacitor 191 holds the following voltage:
(Vfxe2x88x92xcex94V1xe2x88x92xcex94V2)xe2x88x92(Vrefxe2x88x92xcex94V2)=Vfxe2x88x92Vrefxe2x88x92xcex94V1.
Subsequently, by turning on the switch 194 and turning on the switch 190 at a time t2 within the horizontal blanking period (shown in FIGS. 20A and 20C), the potential at the (V2) portion becomes a reset signal Vd of the pixel and thereafter Vdxe2x88x92xcex94V1 if the switch 190 is turned off. In this case, the potential at the (V3) portion is floating in terms of direct current, and therefore, the potential at the (V3) portion is shifted from the (V2) voltage by a voltage difference retained in the capacitor 191 and becomes the following voltage:
(Vdxe2x88x92xcex94V1)xe2x88x92(Vfxe2x88x92Vrefxe2x88x92xcex94V1)=Vref+(Vdxe2x88x92Vf).
That is, the feedthrough level xcex94V1 of the switch 190 is canceled, as a consequence of which the net valid signal Vdxe2x88x92Vf, or the difference between the light-receiving signal Vf of the pixel element and the reset signal Vd is obtained as a value with the reference voltage signal Vref added.
However, the amplification type solid state imaging device shown in FIG. 19 has the following problems. That is, the pixel signal is retained in the input of the amplifier circuit 155 and the region continued from the input while the pixel signal of one horizontal line is read. The period of this retention is distributed throughout the period during which the horizontal scanning circuit 160 scans, the period being short in the first pixel and long in the final pixel. Therefore, if a leak current exists in the input region of the amplifier circuit 155, then the retention voltage is lowered by xcex94Vdrp, and this value becomes small in the first pixel and great in the final pixel. That is, in the output signal, a shading-like nonuniformity that is distributed from the left-hand side to the right-hand side of the screen occurs. This also becomes a sort of FPN that significantly impairs the image quality. There somewhat exist a difference between a pair of capacitor 191 and capacitor 192 and a difference between a pair of switch 193 and switch 194, meaning that they are not completely equivalent to each other. Therefore, in the actual operation, a slight variation occurs every vertical signal line 145, meaning that the FPN does not completely disappear.
Accordingly, the object of the present invention is to provide a correlated double sampling circuit that can provide an amplification type solid state imaging device capable of remarkably reducing FPN that accompanies horizontal pixel selection, reducing shading-shaped nonuniformity and obtaining a high-quality image free of FPN with a simple construction and provide an amplification type solid state imaging device employing the circuit.
In order to achieve the aforementioned object, the present invention provides a correlated double sampling circuit comprising:
an input changeover switch that has one input terminal connected to a signal line and the other input terminal receiving a fixed potential and selects and outputs either a signal of the signal line or the fixed potential;
a first clamping means having a clamping capacitor that has one terminal on an input side connected to an output terminal of the input changeover switch and a clamping switch that has one terminal connected to the other terminal on an output side of the clamping capacitor and the other terminal to which a clamping potential is applied;
a first sample hold means having a sample hold switch that has one terminal connected to the terminal of the output side of the clamping capacitor and a sample hold capacitor that has one terminal connected to the other terminal of the sample hold switch; and
a control means for controlling the input changeover switch, the clamping switch and the sample hold switch so as to switch the input changeover switch to the signal line side in a first period, clamp the signal of the signal line in a first half of the first period by the first clamping means, thereafter sample and hold a signal on the output side of the clamping capacitor in the latter half of the first period by the first sample hold means, switch the input changeover switch to the fixed potential side in a second period subsequent to the first period, sample and hold the clamping potential on the output side of the clamping capacitor by the first clamping means with respect to the fixed potential in the first half of the second period and thereafter sample and hold a signal on the output side of the clamping capacitor by the first sample hold means.
According to the above correlated double sampling circuit, the net signal is obtained as a difference between the first half signal and the latter half signal in the sample hold capacitor through the first correlated double sampling operation (referred to as a CDS operation hereinafter) by the first clamping means and the first sample hold means in the first period during which the input changeover switch is switched to the signal line side. Next, the reference signal including the same feedthrough level as that of the first CDS operation is obtained by in the sample hold capacitor through the second CDS operation by the first clamping means and the first sample hold means in the second period during which the input changeover switch is switched to the fixed potential side. Therefore, by subsequently taking the difference between the signals held in the sample hold capacitor before and after the second sample hold operation, there is obtained only the net signal component in which all the feedthrough levels generated through the CDS operation are removed. Therefore, by applying this correlated double sampling circuit to an amplification type solid state imaging device, the FPN accompanying the horizontal pixel selection can be remarkably reduced with a simple construction and the shading-like nonuniformity can be reduced, allowing a high-quality image free of FPN to be obtained.
In one embodiment, a capacitance of the clamping capacitor is ten or more times greater than a capacitance of the sample hold capacitor.
According to the above correlated double sampling circuit, the capacitance of the clamping capacitor is made ten or more times greater than the capacitance of the sample hold capacitor. With this arrangement, the gain in the case where the signal obtained through the clamping capacitor is accumulated in the sample hold capacitor can be increased.
In one embodiment, the clamping switch and the sample hold switch are each comprised of a MOS transistor, and
a ratio of a sum of areas of a junction section of the clamping switch and a junction section of the sample hold switch respectively connected to the clamping capacitor with respect to the capacitance of the clamping capacitor is substantially equal to a ratio of an area of a junction section of the sample hold switch connected to the sample hold capacitor with respect to the capacitance of the sample hold capacitor.
According to the above correlated double sampling circuit, the ratio of a sum of areas of a junction section of the clamping switch and a junction section of the sample hold switch respectively connected to the clamping capacitor with respect to the capacitance of the clamping capacitor is made substantially equal to the ratio of an area of a junction section of the sample hold switch connected to the sample hold capacitor with respect to the capacitance of the sample hold capacitor. With this arrangement, an equal reduction in potential due to the leak current of the MOS transistors occurs on the signal line between the clamping capacitor and the sample hold capacitor and the signal line on the output side of the sample hold capacitor. Therefore, the reduction in potential due to the leak current of the MOS transistor can be reliably removed through the aforementioned CDS operation.
One aspect of the present invention provides an amplification type solid state imaging device that has a photoelectric conversion means, an amplification type pixel element for amplifying and outputting a light-receiving signal formed by the photoelectric conversion means and a reference signal that serves as a reference of the light-receiving signal, a vertical signal line to which an output of the pixel element is connected, an amplifying means for amplifying a signal of the vertical signal line and a horizontal signal line to which an output of the amplifying means is connected via a horizontal selection switch and transmits the signal of the pixel element to the horizontal signal line via the vertical signal line, the amplifying means and the horizontal selection switch, the amplification type solid state imaging device comprising:
the correlated double sampling circuit provided between the vertical signal line and the amplifying means.
According to the above embodiment, the difference between the light-receiving signal of the pixel element and the reference signal is obtained on the input side of the amplifying means of each vertical signal line through the first CDS operation by the first clamping means and the first sample hold means of the correlated double sampling circuit in the first period. Thereafter, the reference signal including the same feedthrough level as that of the first CDS operation is obtained on the input side of the amplifying means through the second CDS operation by the first clamping means and the first sample hold means in the second period. Therefore, by subsequently taking the difference between the differential signal and the reference signal at the terminal of the horizontal signal line through the CDS operation, there is obtained only the net signal component in which all the feedthrough levels are canceled. Therefore, the FPN accompanying the horizontal pixel selection can be remarkably reduced with a simple construction and the shading-like nonuniformity can be reduced, allowing an amplification type solid state imaging device capable of obtaining a high-quality image free of FPN to be achieved.
In one embodiment, the input changeover switch is switched to the vertical signal line in the first period; either one of the light-receiving signal of the pixel element or the reference signal is clamped in the first half of the first period by the first clamping means, thereafter a signal that represents a difference between the light-receiving signal from the pixel element and the reference signal by a quantity of change from the clamping potential is held on sample hold capacitor by sampling and holding the other one of the light-receiving signal of the pixel element and the reference signal in the latter half of the first period via the clamping capacitor by the first sample hold means, and
the input changeover switch is switched to the fixed potential side in the second period, the clamping potential is sampled and held on the output side of the clamping capacitor by the first clamping means with respect to the fixed potential in the first half of the second period, thereafter a first output signal that represents a difference between the light-receiving signal from the pixel element and the reference signal by a quantity of change from the clamping potential is outputted to the horizontal signal line via the amplifying means in the first half of the period during which the horizontal selection switch is made conductive and the output signal of the amplifying means is read to the horizontal signal line, thereafter the signal on the output side of the clamping capacitor is sampled and held by the first sample hold means and a second output signal that becomes the clamping potential is outputted to the horizontal signal line via the amplifying means in the latter half of the period during which the horizontal selection switch is conductive after the sampling and holding.
According to the above amplification type solid state imaging device, the input changeover switch is switched to the signal line side in the first period, and either one of the light-receiving signal of the pixel element and the reference signal is clamped by the first clamping means in the first half of the first period. Next, the other one of the light-receiving signal of the pixel element and the reference signal in the latter half of the first period is sampled and held by the first sample hold means via the clamping capacitor, and the signal that represents the difference between the light-receiving signal from the pixel element and the reference signal by the quantity of change from the clamping potential is held in the sample hold capacitor. Thereafter, the input changeover switch is switched to the fixed potential side in the second period, and the clamping potential is sampled and held on the output side of the clamping capacitor by the first clamping means with respect to the fixed potential in the early stage of the second period. Next, the first output signal that represents the difference between the light-receiving signal from the pixel element and the reference signal by the quantity of change from the clamping potential is outputted to the horizontal signal line via the amplifying means in the first half of the period during which the horizontal selection switch becomes conductive to read the output signal of the amplifying means to the horizontal signal line. Thereafter, the signal on the output side of the clamping capacitor is sampled and held by the first sample hold means, and the second output signal that represents the clamping potential is outputted to the horizontal signal line in the latter half of the period during which the horizontal selection switch is conductive after the sample hold operation. By taking the difference between the thus obtained first and second output signals, the difference between the light-receiving signal and the reference signal can be obtained.
One embodiment comprises a second clamping means for clamping the first output signal out of a pair of first output signal and second output signal from the horizontal signal line and outputting a signal of difference between the first output signal and the second output signal in the period of outputting the second output signal; and
a second sample hold means for sampling and holding the signal of difference from the second clamping means and outputting the signal of difference that has been sampled and held.
According to the above amplification type solid state imaging device, the signal of difference between a pair of first output signal and second output signal to be read on the horizontal signal line, i.e., the difference between the light-receiving signal from the pixel element and the reference signal can be obtained by the structure of the second clamping means and the second sample hold means. Therefore, a signal which represents an image free of FPN and from which all the variation components are removed can be obtained.
One embodiment comprises a third sample hold means for sampling and holding the first output signal out of a pair of first output signal and second output signal from the horizontal signal line;
a fourth sample hold means for sampling and holding the second output signal out of a pair of first output signal and second output signal from the horizontal signal line; and
a calculating means for obtaining a signal of difference between the first output signal held by a third sample hold means and the second output signal held by a fourth sample hold means and outputting the signal of difference.
According to the above amplification type solid state imaging device, the signal of difference between a pair of first output signal and second output signal to be read on the horizontal signal line, i.e., the difference between the light-receiving signal from the pixel element and the reference signal can be obtained by the structure for taking the difference between the outputs of the third and fourth sample hold means by the calculating means. Therefore, a signal which represents an image free of FPN and from which all the variation components are removed can be obtained.
In one embodiment, the control means outputs a first control signal that is turned on in the latter half of the first period and a second control signal that is turned on in the period during which the horizontal selection switch becomes conductive within the second period, and the imaging device comprises:
a sample hold changeover switch that has one input terminal receiving the first control signal, the other input terminal receiving the second control signal and an output terminal connected to a control input terminal of the sample hold switch of the first sample hold means.
According to the above amplification type solid state imaging device, the sample hold changeover switch is switched to the first control signal side in the latter half of the first period, and the sample hold changeover switch is switched to the second control signal side in the period during which the horizontal selection switch becomes conductive within the second period. This arrangement allows the sample hold switch of the first sample hold means to be controlled for each of the vertical signal lines of which the horizontal selection switches are made sequentially conductive, with a simple construction.
In one embodiment, all the horizontal selection switches are conductive in a period during which the first sample hold means executes sampling and holding within the first period, and
the horizontal selection switch connected to the first sample hold means is conductive in a period during which the first sample hold means samples and holds the signal on the output side of the clamping capacitor within the second period.
According to the above correlated double sampling circuit, the horizontal selection switch becomes conductive in the period during which the first sample hold means executes sampling and holding within both the first and second periods, and the output of the amplifying means is connected to the horizontal signal line via the horizontal selection switch. With this arrangement, the state on the load side of the first sample hold means becomes identical during the operation of the first sample hold means within the first and second periods, meaning that an identical operating condition is provided for each of the two operations. Therefore, FPN and shading-like nonuniformity can be more completely reduced.
In one embodiment, a constant current load that is connected to the horizontal signal line via a load connection switch is provided, and
the load connection switch is off at least in a period during which all the horizontal selection switches are conductive.
According to the above correlated double sampling circuit, the load connection switch is turned off at least in the period during which all the horizontal selection switches are conductive, disconnecting the constant current source from the horizontal signal line. With this arrangement, no load current flows. Accordingly, there is generated no mutual interference even if a great difference in level exists between the outputs of the amplifying means. Therefore, a correct sample hold operation can be executed in each of the two operations without exerting any influence on the sample hold capacitor on the input side of the amplifying means, by which FPN and shading-like nonuniformity can be more completely reduced.
In one embodiment, all the horizontal selection switches are nonconductive at least in a period during which the first sample hold means executes sampling and holding within the first period, and
the horizontal selection switch connected to the first sample hold means is nonconductive in a period during which the first sample hold means samples and holds the signal on the output side of the clamping capacitor within the second period.
According to the above correlated double sampling circuit, the horizontal selection switches become nonconductive when the first sample hold means executes sampling and holding within both the first and second periods, and the output of the amplifying means is not connected to the horizontal signal line via the horizontal selection switch. With this arrangement, the state on the load side of the first sample hold means becomes identical during the operation of the first sample hold means within the first and second periods, meaning that an identical operating condition is provided for each of the two operations. Therefore, FPN and shading-like nonuniformity can be more completely reduced.